Solid-state image sensing device and camera system with divided pixels

ABSTRACT

A solid-state image sensing device includes: a pixel part in which pixels are arranged in a matrix; and a pixel signal readout part including an AD conversion part that analog-digital (AD)-converts a pixel signal read out from the pixel part. Each of the adjacent pixels or one of the pixels of the pixel part is formed as divided pixels divided into regions with different photosensitivity or amounts of accumulated charge, photosensitivity or exposure time conditions are set for the divided pixels and the photosensitivity or exposure time conditions of the divided pixels provided to be opposed in diagonal directions are set to the same conditions, the pixel signal readout part reads out divided pixel signals of the respective divided pixels of the pixel, and the AD conversion part obtains a pixel signal of one pixel by AD-converting the respective read out divided pixel signals and adding the signals.

CROSS REFERENCES TO RELATED APPLICATIONS

This is a Continuation of application Ser. No. 14/529,573, filed on Oct.31, 2014, which is a Continuation of application Ser. No. 13/317,017,filed on Oct. 7, 2011. The present invention contains subject matterrelated to Japanese Patent Application JP 2010-250328, filed in theJapanese Patent Office on Nov. 8, 2010, the entire contents of which areincorporated herein by reference.

FIELD

The present disclosure relates to a solid-state image sensing devicerepresented by a CCD or CMOS sensor and a camera system.

BACKGROUND

It has been desired to realize a solid-state image sensing device havinga wide dynamic range that may enable shooting of details without losingdetails of high-brightness information even in backlit shooting withillumination light of headlights of cars and ball game grounds orsunlight or bringing an object image in the low-brightness part too muchdarker.

Under the circumstances, technologies of expanding dynamic ranges withrespect to solid-state image sensing device such as CCDs are disclosedin Patent Document 1 (Japanese Patent No. 2125710), Patent Document 2(JP-A-03-117281), Patent Document 3 (JP-A-09-205589), Patent Document 4(JP-A-2004-320119), Patent Document 5 (JP-A-2005-278135), PatentDocument 6 (JP-A-2010-284213), etc.

Patent Document 1 shows an example of expanding a dynamic range of a CCDby providing two or more plural regions (cells) having differentsensitivity characteristics within one pixel of the CCD or the like toprovide knee characteristics that input/output characteristics change ina stepwise fashion.

The knee characteristics refer to a characteristic curve shown by arelationship of the output current to the amount of exposure takessmaller values in a high-input region than those in a low-input region,and are often referred to as a high-brightness signal compressiontechnology.

As methods of changing the photosensitivity of the photosensitive region(cell), for example, changing the aperture ratio of the device,providing an optical filter (ND filter), changing impurityconcentration, etc. are described.

According to Patent Document 1, the example is applicable to an imagesensing device of XY address-type other than the CCD, however, there isno detailed description.

Patent Document 2 discloses an example of realizing higher dynamic rangewithout losing details with highlight of a light valve or the like usingadjacent pixels in a photosensitive pixel cell of a CCD or cells withdifferent photosensitivity characteristics as a pair and adding signalcharge of the respective cells within one pixel using it as signalcharge of the pixel.

In this case, as means for changing photosensitivity, cells withdifferent pixel areas are paired, for example.

Patent Document 3 similarly divides one pixel of a sensitivity pixelcell of a CCD into two different regions, and mixes signal charge of theregions with different sensitivity of the same pixel in a verticalregister and vertically transfers it. Further, in the technology, avideo signal is formed by sorting the signal charge with differentsensitivity into two horizontal transfer gates using a sorting gate, andclipping the signal at the high-sensitivity side using an externalsignal processing circuit and adding it to the signal at thelow-sensitivity side.

In this case, the characteristic graph of the video signal output to theamount of incident light is a line graph, and the gradient is steep atthe high-sensitivity side (low-illuminance side) and the gradient ismild at the low-sensitivity side (high-illuminance side).

Patent Document 4 discloses an improvement method, in an image sensingdevice including high-sensitivity imaging cells and low-sensitivityimaging cells, for a problem that RAW image data volume (raw data)becomes larger with data of both cells.

Specifically, whether or not recording of image information of thehigh-brightness part is necessary is automatically determined byanalyzing shot image information. If the determination is “YES”, the RAWimage data of the high-brightness part is recorded together with theinformation of the low-brightness part. If the determination is “NO”,the information of the high-brightness part is not recorded, but onlythe RAW image data of the low-brightness part is recorded.

One pixel is formed by combining a main photosensitive pixel cell (withlarger area and higher sensitivity: mainly using the center part of amicrolens) and a sub-photosensitive pixel cell (with smaller area andlower sensitivity: provided at the edge side of the microlens).

Patent Document 5 discloses a CMOS image sensor including acolumn-parallel ADC having a comparator and an up/down counter. The CMOSimage sensor can execute addition operation of pixel digital values overplural rows without additional circuits such as an adder and a linememory device.

However, compared to the pixel having an area as a total of all areas oftarget pixels in the case of the divided pixel addition, in the case ofdivision, ineffective regions (dead spaces) that do not directlycontribute to photosensitivity are produced in signal processing.

Accordingly, the areas of the divided individual cells are smaller thanin the case of simple division into four, the number of saturatedelectrons decreases compared to the former case and the Shot noiserelatively increases, and S/N of the divided individual cells isdeteriorated.

Since the Shot noise is also added at each time of addition, S/N of theresult of the divisional addition is deteriorated.

Further, addition processing of pixel signals is analog signal additionand the sensitivity is different with respect to each pixel, and thus,there are problems that the saturation values vary and the break pointpositions vary.

Furthermore, in the case of digital addition, it is necessary to providea memory outside of the sensor.

That is, in the existing addition method of dividing one pixel cell intotwo or more plural pixel cells with different sensitivity oraccumulation times and measuring the sensitivity as the amount ofsaturation charge Qs of the pixels, the amount of saturation charge Qsvaries with respect to each pixel. Accordingly, the addition resultvaries with respect to each pixel for the same amount of light.

In other words, in the sensitivity curves (line graphs) with the amountof incident light as a horizontal axis and the amount of saturationcharge Qs as a vertical axis, the break point positions (vertical axis)vary at the divided pixel cell addition points (horizontal axis).

Accordingly, Patent Document 6 suggests a method of realizing a widedynamic range by applying a technology of regarding four pixels as onepixel and varying respective accumulation times of the four pixels. Inthis technology, four signals are added.

FIG. 1 is a diagram for explanation of a method of realizing a widedynamic range by varying respective accumulation times of four pixels.

In the method, pixels formed by respectively dividing single colors ofR, G, B into four are used.

Further, as shown by signs A to D in G (green) on the upper left of FIG.1 as an example, a structure having four pixels with differentphotosensitivity or amounts of exposure is assumed. In FIG. 1, FD showsa floating diffusion part.

Furthermore, by summing the outputs of the four pixels, a wide dynamicrange is realized.

According to the technology, divided pixel addition without variationsin the number of output electrons of pixels may be realized, and thewide dynamic range in which the sensitivity is higher in the loweramount of incident light, the sensitivity is lower with the higherincident light, and the output is not saturated can be provided.

SUMMARY

However, the technology disclosed in Patent Document 6 has the followingdisadvantages.

The centers of gravity are different among the respective pixels andcorrection of shifts of the centers of gravity may be necessary.

As shown in FIG. 2, depending on the computation when the output signalis returned to be linear as from line X to line Y, S/N may not bemaximized.

The problem of shifts of the centers of gravity will be explainedfurther in detail.

When sensitivity/exposure is varied among four pixels, the centers ofgravity vary among four pixels and the correction of shifts of thecenters of gravity is necessary.

When the sensitivity/exposure is simply varied between two pixels, thecenters of gravity vary among two pixels and the correction of shifts ofthe centers of gravity is also necessary.

Due to the difference in the centers of gravity, there may be thefollowing disadvantages.

If the centers of gravity are different, the correction of shifts of thecenters of gravity is necessary, and additionally, for example, when anobject in the lateral direction like electric cables is shot usingpixels with sensitivity/accumulation divided in the vertical directionas shown in FIG. 3, images obtained by the upper pixels and the lowerpixels may be varied.

This may cause generation of false color or noise.

Next, the problem of S/N will be further described in detail.

When signals are formed from four pixels having differentsensitivity/amounts of exposure, it is necessary that the final outputvalue is linear relative to the amount of light as shown by Y in FIG. 2.

It is necessary that the obtained raw (Raw) signal value is made linearas shown by the line Y because the line is folded in the regions RG1 toRG4 in FIG. 2.

As a computation method in this regard, the following example isconceivable.

Region “RG1” Expression: y=ax

Region “RG2” Expression: y′=cx+d

-   -   (x=obtained signal value, y=final output)

In this case, to superimpose the “RG1” Expression on the “RG2”Expression, the “RG2” Expression may be made linear with respect to the“RG1” Expression by subtracting intercept d from “RG2” Expression forsetting the intercept to zero, and multiplying by a/c.

However, in consideration of S (Signal)/N (Noise), regarding theinterception d subtracted in this case, only S (Signal) is subtractedand both Signal and Noise are multiplied by a/c for multiplication(because Subtraction may be impossible for Noise).

Accordingly, S/N is largely deteriorated compared to that beforecomputation.

Thus, it is desirable to provide a solid-state image sensing device anda camera system that may prevent shifts of the centers of gravity,maximize S/N, realize divided pixel addition without variations in thenumber of output electrons of pixels with respect to the amount ofincident light, and have a wide dynamic range in which sensitivity ishigher with a lower amount of incident light and sensitivity is lowerwith high incident light, and the output is not saturated.

A solid-state image sensing device according to one embodiment of thepresent disclosure includes a pixel part in which plural pixels arearranged in a matrix, and a pixel signal readout part including an ADconversion part that analog-digital (AD)-converts a pixel signal readout from the pixel part, wherein each of the plural adjacent pixels orone of the pixels of the pixel part is formed as plural divided pixelsdivided into regions with different photosensitivity or amounts ofaccumulated charge, plural photosensitivity or exposure time conditionsare set for the plural divided pixels and the photosensitivity orexposure time conditions of the divided pixels provided to be opposed indiagonal directions are set to the same conditions, the pixel signalreadout part reads out divided pixel signals of the respective dividedpixels of the pixel, and the AD conversion part obtains a pixel signalof one pixel by AD-converting the respective read out divided pixelsignals and adding the signals.

A solid-state image sensing device according to another embodiment ofthe present disclosure includes a pixel part in which plural pixels arearranged in a matrix, a pixel signal readout part including an ADconversion part that analog-digital (AD)-converts a pixel signal readout from the pixel part, and a processing part that obtains a finaloutput by obtaining an optimal multiplying factor from an output valueof the pixel signal readout part and multiplying the output value by theobtained multiplying factor, wherein each of the plural adjacent pixelsor one of the pixels of the pixel part is formed as plural dividedpixels divided into regions with different photosensitivity or amountsof accumulated charge, the pixel signal readout part reads out dividedpixel signals of the respective divided pixels of the pixel, and the ADconversion part obtains a pixel signal of one pixel by AD-converting therespective read out divided pixel signals and adding the signals.

A camera system according to still another embodiment of the presentdisclosure includes a solid-state image sensing device, and an opticalsystem that forms an object image on the solid-state image sensingdevice, the solid-state image sensing device including a pixel part inwhich plural pixels are arranged in a matrix, and a pixel signal readoutpart including an AD conversion part that analog-digital (AD)-converts apixel signal read out from the pixel part, wherein each of the pluraladjacent pixels or one of the pixels of the pixel part is formed asplural divided pixels divided into regions with differentphotosensitivity or amounts of accumulated charge, pluralphotosensitivity or exposure time conditions are set for the pluraldivided pixels and the photosensitivity or exposure time conditions ofthe divided pixels provided to be opposed in diagonal directions are setto the same conditions, the pixel signal readout part reads out dividedpixel signals of the respective divided pixels of the pixel, and the ADconversion part obtains a pixel signal of one pixel by AD-converting therespective read out divided pixel signals and adding the signals.

A camera system according to yet another embodiment of the presentdisclosure includes a solid-state image sensing device, and an opticalsystem that forms an object image on the solid-state image sensingdevice, the solid-state image sensing device including a pixel part inwhich plural pixels are arranged in a matrix, a pixel signal readoutpart including an AD conversion part that analog-digital (AD)-converts apixel signal read out from the pixel part, and a processing part thatobtains a final output by obtaining an optimal multiplying factor froman output value of the pixel signal readout part and multiplying theoutput value by the obtained multiplying factor, wherein each of theplural adjacent pixels or one of the pixels of the pixel part is formedas plural divided pixels divided into regions with differentphotosensitivity or amounts of accumulated charge, the pixel signalreadout part reads out divided pixel signals of the respective dividedpixels of the pixel, and the AD conversion part obtains a pixel signalof one pixel by AD-converting the respective read out divided pixelsignals and adding the signals.

According to the embodiments of the present disclosure, shifts of thecenters of gravity can be prevented and S/N can be maximized, anddivided pixel addition without variations in the number of outputelectrons of the pixels with respect to the amount of incident light maybe realized. As a result, the wide dynamic range in which thesensitivity is higher in the lower amount of incident light, thesensitivity is lower with the higher incident light, and the output isnot saturated can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram for explanation of a method of realizing a widedynamic range by varying respective accumulation times of four pixels.

FIG. 2 is a diagram showing relationships between raw (Raw) output andfinal output after computation for consideration of a problem of S/N inthe method of realizing a wide dynamic range by varying respectiveaccumulation times of four pixels.

FIG. 3 is a diagram for consideration of a problem due to variations ofcenters of gravity in the method of realizing a wide dynamic range byvarying respective accumulation times of four pixels.

FIG. 4 is a diagram showing a configuration example of a CMOS imagesensor (solid-state image sensing device) according to an embodiment ofthe present disclosure.

FIG. 5 is a diagram showing Bayer arrangement as a pixel arrangementexample.

FIG. 6 is a conceptual diagram of pixel division according to theembodiment.

FIG. 7 is a diagram showing locations where addition processing isperformed in the solid-state image sensing device (CMOS image sensor)with column-parallel ADC in FIG. 1.

FIG. 8 is a diagram for explanation of a two-pixel diagonal method asthe first measure for shifts of the centers of gravity according to theembodiment.

FIG. 9 is a diagram for explanation of a two-pixel diagonal Gr/Gbinversion method as the second measure for shifts of the centers ofgravity according to the embodiment.

FIG. 10 is a diagram for explanation of an application example of thetwo-pixel diagonal Gr/Gb inversion method as the second measure forshifts of the centers of gravity according to the embodiment.

FIG. 11 is a diagram for explanation of measures for S/N according tothe embodiment.

FIG. 12 is a diagram showing an example of a divided pixel of the CMOSimage sensor including four transistors according to the embodiment.

FIG. 13 is a circuit diagram showing an example of the plural dividedpixels sharing floating diffusion parts, amplifying transistors,selection transistors, reset transistors.

FIG. 14 is a circuit diagram showing an example of the plural dividedpixels individually having floating diffusion parts and sharing anamplifying transistors.

FIG. 15 is a circuit diagram showing an example of plural divided pixelsgrouped and sharing floating diffusion parts in the respective groupsand sharing an amplifying transistor in the pixels as a whole.

FIGS. 16A to 16D are diagrams for explanation of methods of divisioninto plural regions within a surface of one pixel.

FIGS. 17A and 17B are diagrams schematically showing configurationexamples of column AD conversion type CMOS image sensor circuits relatedto divided pixel addition.

FIG. 18 is a diagram showing a configuration example of a solid-stateimage sensing device corresponding to a CCD sensor according to theembodiment of the present disclosure.

FIG. 19 is a diagram showing an example of a configuration of a camerasystem to which the solid-state image sensing device according to theembodiment of the present disclosure is applied.

DETAILED DESCRIPTION

As below, embodiments of the present disclosure will be explained withreference to the drawings.

The explanation will be made in the following order.

1. Overall Schematic Configuration of Solid-state Image Sensing Device2. Measures for Shifts of Centers of Gravity 3. Measures for S/N 4.Configuration Example of Divided Pixel 5. Configuration Example ofCamera System <1. Overall Schematic Configuration of Solid-State ImageSensing Device>

FIG. 4 is a block diagram showing a configuration example of asolid-state image sensing device (CMOS image sensor) with columnparallel ADC according to an embodiment of the present disclosure.

The disclosure is applicable not only to the CMOS image sensor but to aCCD. Here, the CMOS image sensor will be explained as an example.

The solid-state image sensing device 100 has a pixel part 110, avertical scan circuit 120, a horizontal transfer scan circuit 130, atiming control circuit 140, and an analog digital converter (ADC) group150 as shown in FIG. 4.

The solid-state image sensing device 100 further has a digital-analogconverter (DAC) 160, an amplifier circuit (S/A) 170, a signal processingcircuit 180, and a horizontal transfer line 190.

The vertical scan circuit 120, the horizontal transfer scan circuit 130,the timing control circuit 140, the ADC group 150, and the DAC 160 forma pixel signal readout part.

The pixel part 110 includes plural pixels arranged in a matrix.

The pixel part 110 employs Bayer arrangement as shown in FIG. 2, forexample, as its pixel arrangement.

In the pixel part 110 of the embodiment, one pixel is divided intodivided pixel cells DPC containing photoelectric conversion elementsformed by photodiodes.

Specifically, in the solid-state image sensing device (CMOS imagesensor) with column parallel ADC 100, one pixel under color filters ofthe same color in the Bayer arrangement is divided into two or moreplural divided pixel cells DPC with different sensitivity oraccumulation times.

Further, in the embodiment, as will be described later, for preventionof shifts of the centers of gravity, a structure under two conditions ofexposure time conditions (or photosensitivity) with pixels opposed toeach other in the diagonal direction having the same exposure time (orphotosensitivity) is employed.

Further, in the embodiment, to maximize S/N, a configuration in which,when the signal is returned to be linear, the signal is not directlyobtained by computation, but the final output is obtained by oncecalculating an optimal multiplying factor from a raw (Raw) output valueand multiplying the raw (Raw) output value by the multiplying factor isemployed.

Furthermore, when the pixel signal is AD-converted and output in thecolumn direction, the AD-conversion is performed after addition of theoutput divided pixel signal of the divided pixel. In this regard, theinput range to the AD-conversion part is clipped to be constantly equalto or less than the saturated output voltage of each pixel so that theoutput value of each pixel may be certainly a specific digital value.

In the following explanation, an example in which one pixel DPC isdivided into four divided pixel cells DPC-A to DPC-D will be explained.

FIG. 6 is a conceptual diagram of pixel division according to theembodiment of the present disclosure.

FIG. 6 shows the case where a G (green) pixel PCG is divided into fourpixels of DPC-A, DPC-B, DPC-C, DPC-D.

In FIG. 6, a division method in the case of Bayer arrangement is shown,and, in the example in which one pixel under the filters of the samecolor is divided into four, sensitivity and accumulation times aredifferent in the divided pixels as below.

That is, for prevention of shifts of the centers of gravity, there aretwo conditions of exposure time conditions (or photosensitivity) andpixels opposed to each other in the diagonal directions have the sameexposure times (or photosensitivity).

For example, in the example of the G pixel in FIG. 6, the pixels opposedto each other in the diagonal directions DPC-A and DPC-C, DPC-B andDPC-D have the same exposure times.

The configurations, division forms, etc. of the pixels and dividedpixels in the pixel part 110 will be described later in detail.

Further, for example, the solid-state image sensing device 100 of theembodiment time-sequentially sends out divided pixel signals amplifiedwithin the pixel to the vertical signal line and executes AD-conversionin the AD-convertor (AD-conversion part) of the ADC group 150 providedin a column pixel signal readout part.

Then, when performing the AD-conversion operation of the second dividedpixel signal, the solid-state image sensing device 100 adds the firstAD-converted value and executes the AD-conversion operation of thesecond divided pixel signal.

Then, when performing the AD-conversion operation of the third dividedpixel signal, the solid-state image sensing device 100 adds the secondAD-converted value and executes the AD-conversion operation of the thirddivided pixel signal.

Then, when performing AD-conversion operation of the fourth dividedpixel signal, the solid-state image sensing device 100 adds the thirdAD-converted value and executes the AD-conversion operation of thefourth divided pixel signal.

The solid-state image sensing device of the embodiment employs a dividedpixel addition method of sequentially adding the pixel signals of thepixels divided into plural parts by the AD converter provided in thecolumn part in this manner is employed.

In the solid-state image sensing device 100, as control circuits forsequentially reading out the signals of the pixel part 110, the timingcontrol circuit 140 that generates internal clocks, the vertical scancircuit 120 that controls row addresses and row scanning, and thehorizontal transfer scan circuit 130 that controls column addresses andcolumn scanning are provided.

The ADC group 150 has a comparator 151 that compares a reference voltageVslop as a ramp waveform in which the reference voltage generated by theDAC 160 is changed in a stepwise manner with analog signals (potentialsVsl) obtained from pixels with respect to each row via the verticalsignal line LVS.

In the ADC group 150, ADCs each having an up-down counter (hereinafter,simply referred to as “counter”) 152 that counts a comparison time and alatch 153 that holds a count result are arranged in plural columns.

The ADC group 150 has an n-bit digital signal conversion function and isprovided with respect to each vertical signal line (column line), andthereby, a column-parallel AD block is formed.

The outputs of the respective latches 153 are connected to thehorizontal transfer line 190 having a 2n-bit width, for example.

Further, 2n amplifier circuits 170 corresponding to the horizontaltransfer line 190 and the signal processing circuit 180 are provided.

In the ADC group 150, the analog signal (potential Vsl) read out to thevertical signal line LVS is compared with the reference voltage Vslop (aslope waveform that changes to a linear shape with a certain gradient)in the comparator (comparator) 151 provided with respect to each column.

In this regard, the counter 152 provided with respect to each columnsimilarly to the comparator 151 operates and the potential Vslop havingthe ramp waveform and the counter value change in one-to-onecorrespondence, and thereby, the potential (analog signal) Vsl of thevertical signal line LVS is converted into the digital signal.

The change of the reference potential Vslop is conversion of change involtage into change in time, and the ADC performs conversion into adigital value by counting the times in a certain period (clock).

Further, when the analog electric signal Vsl and the reference voltageVslop intersect, the output of the comparator 151 is inverted, the inputclock of the counter 152 is stopped or the clock with its input havingbeen stopped is input to the counter 152, and thereby, one AD conversionis completed.

For example, by continuously performing the up and down count processingof the counter in the number of divided pixel signals without resettingthe counter, the divided pixel addition as addition by the abovedescribed AD convertor is realized.

FIG. 7 is a diagram showing locations where addition processing isperformed in the solid-state image sensing device (CMOS image sensor)with column-parallel ADC in FIG. 4.

In FIG. 7, the locations surrounded by broken lines are locations whereaddition processing is actually performed. A thin broken line is anexisting location and a thick broken line is a region according to theembodiment of the present disclosure.

The method of addition signal processing of the divided pixels that hasbeen known is performed in the signal processing part of DSP or thelike.

On the other hand, in the embodiment, as described above, additionprocessing is sequentially performed while AD conversion of the fourdivided pixel signal in the counter 152 at AD conversion.

That is, the divided pixel signals amplified within the pixel aretime-sequentially sent out to the vertical signal line VSL, and ADconversion is executed by the AD converter (AD-conversion part) of theADC group 150 provided in the column pixel signal readout part.

Then, in each ADC of the ADC group 150, when the AD-conversion operationof the second divided pixel signal is performed, the first AD-convertedvalue is added and the AD-conversion operation of the second dividedpixel signal is executed.

Then, in each ADC of the ADC group 150, when the AD-conversion operationof the third divided pixel signal is performed, the second AD-convertedvalue is added and the AD-conversion operation of the third dividedpixel signal is executed.

Then, in each ADC of the ADC group 150, when the AD-conversion operationof the fourth divided pixel signal is performed, the third AD-convertedvalue is added and the AD-conversion operation of the fourth dividedpixel signal is executed.

After the above described AD conversion period is ended, by thehorizontal transfer scan circuit 130, the data held in the latches 153are transferred to the horizontal transfer line 190, input to the signalprocessing circuit 180 via the amplifier circuits 170, and thereby, atwo-dimensional image is generated by predetermined signal processing.

As above, the basic configuration and function in the embodiment of thepresent disclosure have been explained.

As below, the configurations and division forms of the pixels anddivided pixels, the measures for shifts of the centers of gravity, themeasures for S/N, divided pixel addition processing, etc. ascharacteristic configurations of the embodiment will be explained infurther detail.

First, the measures for shifts of the centers of gravity and themeasures for S/N as characteristic configurations of the embodiment willbe described.

In the case where photosensitivity and amounts of exposure are differentamong the four pixels DPC-A to DPC-D of the respective pixels of RGB,the centers of gravity are different among the respective pixels, andcorrection of shifts of the centers of gravity may be necessary.

As shown in FIG. 2, depending on the computation when the output signalis returned to be linear as from line X to line Y, S/N may not bemaximized.

Accordingly, in the embodiment, the measures for shifts of the centersof gravity and the measures for S/N described as below are taken.

<2. Measures for Shifts of Centers of Gravity>

FIG. 8 is a diagram for explanation of a two-pixel diagonal method asthe first measure for shifts of the centers of gravity according to theembodiment.

In the two-pixel diagonal method of FIG. 8, two kinds of conditions ofphotosensitivity/amounts of exposure are set so that the respectivediagonal pixels may have the same conditions.

In the example of FIG. 8, in a Gr pixel, the first condition is suchthat the photosensitivity/amounts of exposure of the upper left pixelDPC-A and the lower right pixel DPC-C opposed to each other in thediagonal direction are the same. Similarly, the second condition is suchthat the photosensitivity/amounts of exposure of the upper right pixelDPC-B and the lower left pixel DPC-D opposed to each other in thediagonal direction are the same.

The conditions are the same with respect to other Gb pixels, R pixels,and B pixels.

Regarding these Gr pixel, Gb pixels, R pixels, and B pixels, all of thecenters of gravity of the signals to be finally added in the FD arecollected to the center of the four pixels, and the correction of shiftsof the centers of gravity is unnecessary and strong for linear objectsin the lateral direction and longitudinal direction.

FIG. 9 is a diagram for explanation of a two-pixel diagonal Gr/Gbinversion method as the second measure for shifts of the centers ofgravity according to the embodiment.

In the two-pixel diagonal Gr/Gb inversion method of FIG. 9, thedirection in which the conditions of photosensitivity/amount of exposureof G pixels in the B column and the R column vary is changed.

In the example of FIG. 9, in the Gr pixel, the first condition is suchthat the photosensitivity/amounts of exposure of the upper left pixelDPC-A and the lower right pixel DPC-C opposed to each other in thediagonal direction are the same. In the Gr pixel, the second conditionis such that the photosensitivity/amounts of exposure of the upper rightpixel DPC-B and the lower left pixel DPC-D opposed to each other in thediagonal direction are the same.

In this regard, in the R pixel, the second condition is such that thephotosensitivity/amounts of exposure of the upper left pixel DPC-A andthe lower right pixel DPC-C opposed to each other in the diagonaldirection are the same. In the R pixel, the first condition is such thatthe photosensitivity/amounts of exposure of the upper right pixel DPC-Band the lower left pixel DPC-D opposed to each other in the diagonaldirection are the same.

Further, in the Gb pixel, the second condition is such that thephotosensitivity/amounts of exposure of the upper left pixel DPC-A andthe lower right pixel DPC-C opposed to each other in the diagonaldirection are the same. In the Gb pixel, the first condition is suchthat the photosensitivity/amounts of exposure of the upper right pixelDPC-B and the lower left pixel DPC-D opposed to each other in thediagonal direction are the same.

In this regard, in the B pixel, the first condition is such that thephotosensitivity/amounts of exposure of the upper left pixel DPC-A andthe lower right pixel DPC-C opposed to each other in the diagonaldirection are the same. In the B pixel, the second condition is suchthat the photosensitivity/amounts of exposure of the upper right pixelDPC-B and the lower left pixel DPC-D opposed to each other in thediagonal direction are the same.

In the two-pixel diagonal method, it is considered that the possibilityof shifts of the centers of gravity may slightly remain in the linearobject in the diagonal direction, however, by changing the direction inwhich the conditions of photosensitivity/amounts of exposure of G pixelsin the B column and the R column vary, a layout having resistance in thediagonal directions may be realized.

Note that arrangements strong for false color and noise can be made withrespect to the B signals and R signals by further applying the two-pixeldiagonal Gr/Gb inversion method with a little ingenuity of arrangementin units of pixels of 8×8 as shown in FIG. 10.

<3. Measures for S/N>

FIG. 11 is a diagram for explanation of measures for S/N according tothe embodiment.

In FIG. 11, to facilitate understanding, the signs are the same as thosein FIG. 2 and FIG. 2 may be cited in the explanation.

As explained with reference to FIG. 2, subtraction of the intercept ofthe expression is subtraction of Signal, and deterioration of S/N may becaused.

That is, in the existing method, to obtain the target output from theRaw sensor output, computation is performed directly from the equation.Accordingly, S/N may be deteriorated due to the influence of thesubtraction component (only on Signal) and the multiplication component(also on Noise).

On the other hand, in the embodiment, to prevent S/N deterioration,“multiplying factor for obtaining target value” is once obtained fromthe obtained signal value and computation is performed by “obtainedsignal value×multiplying factor”, and thereby, the intercept (Signal)may be left.

That is, the multiplying factor is calculated from the Raw sensoroutput.

By directly multiplying the Raw sensor output by the multiplying factor(without subtraction), S/N may be maintained.

As described above, “measures for S/N” in the embodiment is a method ofcomputing the signal value after readout of the pixel signal, and themultiplying factor is changed depending on the obtained signal value andoutput.

As a computation method, for example, there is a method havingmultiplying factor tables with respect to each output value or a methodof mathematical computation.

These computations are performed in one system after readout of thepixel signal. For example, the processing may be performed in the signalprocessing circuit 180.

<4. Configuration Example of Divided Pixel>

First, to facilitate understanding, an example of a configuration of abasic divided pixel of the CMOS image sensor will be explained.

FIG. 12 is a diagram showing an example of a divided pixel of the CMOSimage sensor including four transistors according to the embodiment.

The divided pixel DPC1 has a photoelectric conversion element 111 formedby a photodiode, for example.

The divided pixel DPC in FIG. 12 has four transistors of a transfertransistor 112, a reset transistor 113, an amplifying transistor 114 asan amplification part, and a selection transistor 115 as active elementsfor the one photoelectric conversion element 111.

The photoelectric conversion element 111 photoelectrically convertsincident light into charge (here, electrons) in an amount in response tothe amount of light.

The transfer transistor 112 is connected between the photoelectricconversion element 111 and the floating diffusion part FD and a controlsignal Tx is provided to its gate (transfer gate) through a transfercontrol line LTx.

Thereby, the electrons photoelectrically converted by the photoelectricconversion element 111 are transferred to the floating diffusion partFD.

The reset transistor 113 is connected between a power supply line LVDDand the floating diffusion part FD and a control signal RST is providedto its gate through a reset control line LRST.

Thereby, the potential of the floating diffusion part FD is reset to thepotential of the power supply line LVDD.

To the floating diffusion part FD, the gate of the amplifying transistor114 is connected. The amplifying transistor 114 is connected to avertical signal line 116 via the selection transistor 115 and forms asource follower with a constant current source outside of the pixelpart.

Further, a control signal (address signal or select signal) SEL isprovided to the gate of the selection transistor 115 through a selectioncontrol line LSEL and the selection transistor 115 is turned on.

When the selection transistor 115 is turned on, the amplifyingtransistor 114 amplifies the potential of the floating diffusion part FDand outputs a voltage in response to the potential to the verticalsignal line 116. The voltages output from the respective pixels throughthe vertical signal line 116 are output to the ADC group 150 as thepixel signal readout circuit.

These operations are simultaneously performed with respect to therespective divided pixels DPC of one row because, for example, therespective gates of the transfer transistors 112, the reset transistors113, and the selection transistors 115 are connected in units of rows.

The reset control line LRST, the transfer control line LTx, and theselection control line LSEL wired in the pixel part 110 are wired as oneset for the respective rows of the pixel arrangement.

These reset control line LRST, transfer control line LTx, and selectioncontrol line LSEL are driven by the pixel drive circuit 102.

The above described configuration can be applied without change to thedivided pixel cell according to the embodiment.

Further, as a configuration in which each divided pixel cell containsthe photoelectric conversion element and the transfer transistor, aconfiguration in which the divided pixel cells share the floatingdiffusion part FD can be employed.

In this case, the cells can be formed to share the amplifying transistoras the amplification part, the selection transistor, and the resettransistor.

FIG. 13 is a circuit diagram showing an example of the plural dividedpixels sharing floating diffusion parts, amplifying transistors,selection transistors, reset transistors.

For the pixel PC containing plural divided pixels DPC-A to DPC-D in FIG.13, the photoelectric conversion elements 111-A to 111-D and transfertransistors 112-A to 112-D are provided with respect to the dividedpixels DPC-A to DPC-D.

Further, one ends (for example, drains) of the transfer transistors112-A to 112-D are connected to a shared floating diffusion part SFD.

The gate of the transfer transistor 112-A is connected to a transfercontrol line LTxA and the gate of the transfer transistor 112-B isconnected to a transfer control line LTxB. Similarly, the gate of thetransfer transistor 112-C is connected to a transfer control line LTxCand the gate of the transfer transistor 112-D is connected to a transfercontrol line LTxD.

The reset transistor 113 is connected between the power supply potentialVDD and the shared floating diffusion part SFD. The gate of the resettransistor 113 is connected to the reset control line LRST.

The amplifying transistor 114 and the selection transistor 115 areconnected in series between the power supply potential VDD and thevertical signal line 116. Further, the gate of the amplifying transistor114 is connected to the shared floating diffusion part SFD and the gateof the selection transistor 115 is connected to the selection controlline LSEL.

In the configuration, the divided pixel signals photoelectricallyconverted by the photoelectric conversion elements 111-A to 111-D of therespective divided pixels DPC-A to DPC-D are transferred to theamplifying transistor 114 as the amplification part through the sharedfloating diffusion part SFD. Then, the divided pixel signals areamplified and the amplified divided pixel signals are time-sequentiallysent out to the vertical signal line 116.

Further, a configuration in which each divided pixel cell contains thephotoelectric conversion element, the transfer transistor, and the resettransistor and the divided pixel cell individually contains the floatingdiffusion part FD can be employed.

In this case, the cells can be formed to share the amplifying transistoras the amplification part.

FIG. 14 is a circuit diagram showing an example of the plural dividedpixels individually having floating diffusion parts and sharingamplifying transistors.

In the pixel PC containing the plural divided pixels DPC-A to DPC-D ofFIG. 14, the photoelectric conversion elements 111-A to 111-D andtransfer transistors 112-A to 112-D are provided with respect to thedivided pixels DPC-A to DPC-D. Further, in the divided pixels DPC-A toDPC-D, floating diffusion parts FD-A to FD-D and reset transistors 113-Ato 113-D are provided.

The selection transistor 115-A is connected between the floatingdiffusion part FD-A and a node ND1, and the selection transistor 115-Bis connected between the floating diffusion part FD-B and the node ND1.

Similarly, the selection transistor 115-C is connected between thefloating diffusion part FD-C and the node ND1, and the selectiontransistor 115-D is connected between the floating diffusion part FD-Dand the node ND1.

The gate of the transfer transistor 112-A is connected to the transfercontrol line LTxA and the gate of the transfer transistor 112-B isconnected to the transfer control line LTxB. Similarly, the gate of thetransfer transistor 112-C is connected to the transfer control line LTxCand the gate of the transfer transistor 112-D is connected to thetransfer control line LTxD.

The gate of the reset transistor 113-A is connected to the reset controlline LRSTA and the gate of the reset transistor 113-B is connected tothe reset control line LRSTB. Similarly, the gate of the resettransistor 113-C is connected to the reset control line LRSTC and thegate of the reset transistor 113-D is connected to the reset controlline LRSTD.

The gate of the selection transistor 115-A is connected to the selectioncontrol line LSELA and the gate of the selection transistor 115-B isconnected to the selection control line LSELB. Similarly, the gate ofthe selection transistor 115-C is connected to the selection controlline LSELC and the gate of the selection transistor 115-D is connectedto the selection control line LSELD.

The amplifying transistor 114 is connected between the power supplypotential VDD and the vertical signal line 116. Further, the gate of theamplifying transistor 114 is connected to the node ND1.

In the configuration, the divided pixel signals photoelectricallyconverted by the photoelectric conversion elements 111-A to 111-D of therespective divided pixels DPC-A to DPC-D are transferred to the floatingdiffusion parts FD-A to FD-D. The divided pixel signals are transferredto the amplifying transistor 114 as the amplification part through thefloating diffusion parts FD-A to FD-D and further via the selectiontransistors 115-A to 115-D. Then, the divided pixel signals areamplified and the amplified divided pixel signals are time-sequentiallysent out to the vertical signal line 116.

Further, a configuration in which plural divided pixels forming onepixel are divided into plural groups and each divided group shares thefloating diffusion part FD can be employed.

In this case, each divided group can be formed to share the resettransistor and the selection transistor and the groups can be formed toshare the amplifying transistor as a whole.

FIG. 15 is a circuit diagram showing an example of plural divided pixelsgrouped and sharing floating diffusion parts in the respective groupsand sharing an amplifying transistors in the pixel as a whole.

In this example, four divided pixels DPC-A, DPC-B, DPC-C, DPC-D aresegmented into two groups.

Specifically, the divided pixel DPC-A and the divided pixel DPC-B aresegmented into the first group GRP1 and the divided pixel DPC-C and thedivided pixel DPC-D are segmented into the second group GRP2.

For the divided pixels DPC-A and DPC-B of the first group GRP1 in FIG.15, the photoelectric conversion elements 111-A and 111-B and thetransfer transistors 112-A and 112-B are provided, respectively.

Further, one ends (for example, drains) of the transfer transistors112-A and 112-B are connected to a shared floating diffusion part SFD1.

The gate of the transfer transistor 112-A is connected to the transfercontrol line LTxA and the gate of the transfer transistor 112-B isconnected to the transfer control line LTxB.

For the divided pixels DPC-C and DPC-D of the second group GRP2 in FIG.15, the photoelectric conversion elements 111-C and 111-D and thetransfer transistors 112-C and 112-D are provided, respectively.

Further, one ends (for example, drains) of the transfer transistors112-C and 112-D are connected to a shared floating diffusion part SFD2.

The gate of the transfer transistor 112-C is connected to the transfercontrol line LTxC and the gate of the transfer transistor 112-D isconnected to the transfer control line LTxD.

A reset transistor 113-1 is connected between the power supply potentialVDD and a shared floating diffusion part SFD1. The gate of the resettransistor 113-1 is connected to the reset control line LRST1.

A reset transistor 113-2 is connected between the power supply potentialVDD and the shared floating diffusion part SFD2. The gate of the resettransistor 113-2 is connected to a reset control line LRST2.

A selection transistor 115-1 is connected between the shared floatingdiffusion part SFD1 and the node ND2 and a selection transistor 115-2 isconnected between the shared floating diffusion part SFD2 and the nodeND2.

The gate of the selection transistor 115-1 is connected to a selectioncontrol line LSEL1 and the gate of the selection transistor 115-2 isconnected to a selection control line LSEL2.

The amplifying transistor 114 is connected between the power supplypotential VDD and the vertical signal line 116. Further, the gate of theamplifying transistor 114 is connected to the node ND2.

In the configuration, the divided pixel signals photoelectricallyconverted by the photoelectric conversion elements 111-A to 111-D of therespective divided pixels DPC-A to DPC-D are transferred to the sharedfloating diffusion parts SFD1 and SFD2. The divided pixel signals aretransferred to the amplifying transistor 114 as the amplification partthrough the shared floating diffusion parts SFD1 and SFD2 and furthervia the selection transistors 115-1 and 115-2. Then, the divided pixelsignals are amplified and the amplified divided pixel signals aretime-sequentially sent out to the vertical signal line 116.

As described above, there are various methods of division into pluralregions within a surface of one pixel, and the methods are roughlyclassified into a shared floating diffusion (four pixels shared) method(hereinafter, referred to as “shared FD method”) and an individualfloating diffusion method (hereinafter, referred to as “individual FDmethod”).

FIGS. 16A to 16D are diagrams for explanation of methods of divisioninto plural regions within a surface of one pixel.

FIG. 16A shows an example of division into four in square shapes by theshared FD method, FIG. 16B shows an example of division into four insquare shapes by the individual FD method, FIG. 16C shows an example ofdivision into four in reed shapes by the shared FD method, and FIG. 16Dshows an example of division into four in reed shapes by the individualFD method.

Although the detailed explanation is omitted, stacking of photosensitivelayers and semiconductor layers (P-N junction) with differentsensitivity in a direction perpendicular to the surface may be referredto as pixel division in a broad sense.

To change the sensitivity of the divided pixel may be realized bymethods of changing the aperture ratio of the device, providing opticalfilter characteristics to the insulating film on the photosensitiveregion, changing impurity concentration of the substrate, etc.

FIGS. 16A to 16D show specific examples in which one pixel is dividedinto four, and there are ineffective regions (dead spaces) IVL that doesnot directly contribute to photosensitivity in addition to dividedphotosensitive regions PA, PB, PC, PD.

The region IVL is a space (channel stop) for electric isolation so thatthe pixel charge accumulated in the divided cells may not leak out orinterfere with each other, and wiring for signal processing is providedtherein according to need.

In the above explanation, the divided pixel addition signal processinghas been explained by taking the solid-state image sensing device (CMOSimage sensor) with column-parallel ADC as an example.

For the divided pixel addition signal processing of the column ADconversion type CMOS image sensor, for example, the following twomethods can be employed.

FIG. 17A is a diagram schematically showing a configuration example of acolumn AD conversion type CMOS image sensor circuit related to dividedpixel addition.

In FIG. 17A, one pixel under color filters of the same color is dividedinto four and photosensitivity and accumulation times are varied withrespect to each of the plural pixels opposed in the diagonal directionof the respective divided pixels, and pixel signals are sequentiallyread out to the same signal line through the shared floating diffusionpart FD. Then, noise processing is performed by a CDS circuit 200provided with respect to each column and A/D conversion is performed onone row at a time outside of the column.

FIG. 17B is a diagram schematically showing another configurationexample of the column AD conversion type CMOS image sensor circuitrelated to divided pixel addition.

In FIG. 17B, one pixel under color filters of the same color is dividedinto four and photosensitivity and accumulation times are varied withrespect to each of the plural pixels opposed in the diagonal directionof the respective divided pixels. Then, pixel signals are sequentiallyread out to the same signal line through the shared FD, and the firstnoise processing is performed by a CDS circuit 210 provided with respectto each column.

Then, the analog signal is converted into a digital signal by an A/Dconverter 220 similarly provided with respect to each column, the secondnoise processing is performed by a CDS circuit 230 similarly providedwith respect to each column, and thereby, the digital noise generated atA/D conversion is removed.

Further, in the above explanation, the example in which the embodimentof the present disclosure is applied to the CMOS image sensor has beenexplained, however, the embodiment of the present disclosure may beapplied to a CCD sensor.

FIG. 18 is a diagram showing a configuration example of a solid-stateimage sensing device corresponding to a CCD sensor according to theembodiment of the present disclosure.

A solid-state image sensing device 300 in FIG. 18 has plural sensorparts (photoelectric conversion elements) 311 arranged in a matrix inthe row (vertical) direction and the column (horizontal) direction andconvert incident light into signal charge in an amount of charge inresponse to its amount of light and accumulates it.

The solid-state image sensing device 300 has plural vertical transferregisters 312 arranged with respect to each vertical column of thesensor parts 311 and vertically transfer signal charge read out via areadout gate part (not shown) from the respective sensor parts 311. Thesensor parts and the vertical transfer registers 312 form an imagingarea 313.

The sensor part 311 employs Bayer arrangement and the respective pixelsare divided into divided pixels DPC as plural regions with differentsensitivity (for example, four, two for each).

The vertical transfer register 312 is driven for transfer by verticaltransfer pulses for three or four phases, for example, and sequentiallytransfers signal charge as divided pixel signals read out from therespective sensor parts 311 with respect to each part corresponding toone scan line (one line) in a part of a horizontal blanking period.

A horizontal transfer register 314 is provided on the lower side of theimaging area 313 in the drawing. The signal charge as divided pixelsignals corresponding to one line is sequentially transferred from eachof the plural vertical transfer registers 312 to the horizontal transferregister 314.

The horizontal transfer register 314 is driven for transfer by verticaltransfer pulses for three or four phases, for example, and sequentiallytransfers the signal charge for one line transferred from the pluralvertical transfer registers 312 in the horizontal direction in ahorizontal scan period after the horizontal blanking period.

At the end on the transfer destination side of the horizontal transferregister 314, for example, a charge detection part 315 having a floatingdiffusion amplifier configuration is provided.

The charge detection part 315 has a floating diffusion part FD thataccumulates signal charge supplied from the horizontal transfer register314 via a horizontal output gate part. Though not shown, the chargedetection part 315 includes a reset drain (RD) that drains signal chargeand a reset gate (RG) provided between the floating diffusion part FDand the reset drain.

In the charge detection part 315, a predetermined reset drain voltage isapplied to the reset drain and reset pulses are applied to the resetgate with a detection period of signal charge.

Further, the signal charge accumulated in the floating diffusion part FDis converted into a signal voltage and led out to a CSD circuit 320 viaan output circuit 316 as a CCD output signal CCDout. Then, in an ADC330, AD conversion and addition processing of the respective dividedpixel signals are performed.

As explained above, according to the embodiment, for prevention ofshifts of the centers of gravity, a structure under two conditions ofexposure time conditions (or photosensitivity) with pixels opposed toeach other in the diagonal direction having the same exposure time (orphotosensitivity) is employed.

Further, these pixel signals are sent out to the vertical signal lineand added in the AD conversion part provided in the column part.

Furthermore, in the embodiment, to maximize S/N, a configuration inwhich, when the signal is returned to be linear, the signal is notdirectly obtained by computation, but the final output is obtained byonce calculating an optimal multiplying factor from a raw (Raw) outputvalue and multiplying the raw (Raw) output value by the multiplyingfactor is employed.

Therefore, according to the embodiment, the following advantages may beobtained.

Shifts of the centers of gravity can be prevented and S/N can bemaximized.

Pixels of a solid-state image sensing device that has a wide dynamicrange, higher sensitivity with a low amount of light, and ahigh-brightness information compression property may be realized.

Further, an external memory is unnecessary compared to existing digitaladdition.

There are no longer variations of the break point at which one of pixelsas addition targets is saturated as in analog addition.

S/N is improved at the break point (at which one of pixels as additiontargets is saturated) and S/N nearly equal to or more than that of anon-divided pixel may be achieved in the middle or higher brightnessrange.

Furthermore, a divided pixel structure may be realized without muchincrease in the number of processes.

In addition, a configuration in which the respective divided pixels areindependently read out according to the specifications and the readoutmay be switched to readout for obtaining high resolution images can beemployed.

The solid-state image sensing device having the above advantages may beapplied as an imaging device for a digital camera or video camera.

<5. Configuration Example of Camera System>

FIG. 19 is a diagram showing an example of a configuration of a camerasystem to which the solid-state image sensing device according to theembodiment of the present disclosure is applied.

The camera system 400 has an imaging device 410 to which the CMOS imagesensor (solid-state image sensing device) 100, 300 according to theembodiment can be applied as shown in FIG. 19.

The camera system 400 has an optical system that guides incident lightto a pixel region of the imaging device 410 (forms an object image) anda lens 420 that images the incident light (image light) on an imagingsurface, for example.

The camera system 400 has a drive circuit (DRV) 430 that drives theimaging device 410 and a signal processing circuit (PRC) 440 thatprocesses an output signal of the imaging device 410.

The drive circuit 430 has a timing generator (not shown) that generatesvarious timing signals including start pulses and clock pulses thatdrive the circuits within the imaging device 410, and drives the imagingdevice 410 with predetermined timing signals.

Further, the signal processing circuit 440 performs signal processingsuch as CDS on the output signal of the imaging device 410.

The image signal processed in the signal processing circuit 440 isrecorded in a recording medium such as a memory. The image informationrecorded in the recording medium is hard-copied using a printer or thelike. Alternatively, the image signal processed in the signal processingcircuit 440 is displayed as a moving image on a monitor of a liquidcrystal display or the like.

As described above, in an imaging apparatus such as a digital camera, bymounting the above described image sensing device 100 as the imagingdevice 410, a camera with low power consumption and high definition maybe realized.

The present disclosure contains subject matter related to that disclosedin Japanese Priority Patent Application JP 2010-250328 filed in theJapan Patent Office on Nov. 8, 2010, the entire content of which ishereby incorporated by reference.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalents thereof.

What is claimed is:
 1. An imaging device comprising a plurality of pixelgroups, at least one of the pixel groups including: a first floatingdiffusion; a second floating diffusion; a third floating diffusion; afourth floating diffusion; a first photoelectric conversion element; asecond photoelectric conversion element; a third photoelectricconversion element; a fourth photoelectric conversion element; a firsttransfer transistor connected between the first photoelectric conversionelement and the first floating diffusion; a second transfer transistorconnected between the second photoelectric conversion element and thesecond floating diffusion; a third transfer transistor connected betweenthe third photoelectric conversion element and the third floatingdiffusion; a fourth transfer transistor connected between the fourthphotoelectric conversion element and the fourth floating diffusion; andan amplifying transistor, wherein a gate of the amplifying transistor isconnected to the first floating diffusion, the second floatingdiffusion, the third floating diffusion, and the fourth floatingdiffusion.
 2. The imaging device according to the claim 1, wherein theone of the pixel groups further including: a first selection transistorconnected between the gate of the amplifying transistor and the firstfloating diffusion; a second selection transistor connected between thegate of the amplifying transistor and the second floating diffusion; athird selection transistor connected between the gate of the amplifyingtransistor and the third floating diffusion; and a fourth selectiontransistor connected between the ate of the amplifying transistor andthe fourth floating diffusion.
 3. The imaging device according to theclaim 1, wherein the first and the fourth photoelectric conversionelements are arranged along a first direction, and wherein the secondand the third photoelectric conversion elements are arranged along asecond direction,
 4. The imaging device according to the claim 1,wherein the first, the second, the third, and the fourth photoelectricconversion elements are arranged along a first direction.
 5. An imagingdevice comprising a plurality of pixel groups, at least one of the pixelgroups including: a first floating diffusion; a second floatingdiffusion; a first photoelectric conversion element; a secondphotoelectric conversion element; a first transfer transistor connectedbetween the first photoelectric conversion element and the firstfloating diffusion; a second transfer transistor connected between thesecond photoelectric conversion element and the second floatingdiffusion; and an amplifying transistor, wherein a gate of theamplifying transistor is connected to the first floating diffusion andthe second floating diffusion different from the first direction.
 6. Theimaging device according to the claim 5, wherein the one of the pixelgroups further including: a first selection transistor connected betweenthe gate of the amplifying transistor and the first floating diffusion;and a second selection transistor connected between the gate of theamplifying transistor and the second floating diffusion.
 7. An imagingdevice comprising a plurality of pixel groups, at least one of the pixelgroups including: a first floating diffusion; a second floatingdiffusion; a first photoelectric conversion element; a secondphotoelectric conversion element; a third photoelectric conversionelement; a fourth photoelectric conversion element; a first transfertransistor connected between the first photoelectric conversion elementand the first floating diffusion; a second transfer transistor connectedbetween the second photoelectric conversion element and the firstfloating diffusion; a third transfer transistor connected between thethird photoelectric conversion element and the second floatingdiffusion; a fourth transfer transistor connected between the fourthphotoelectric conversion element and the second floating diffusion; andan amplifying transistor, wherein a gate of the amplifying transistor isconnected to the first floating diffusion and the second floatingdiffusion.
 8. The imaging device according to the claim 7, wherein theone of the pixel groups further including: a first selection transistorconnected between the gate of the amplifying transistor and the firstfloating diffusion; and a second selection transistor connected betweenthe gate of the amplifying transistor and the second floating diffusion.9. The imaging device according to the claim 7, wherein the first andthe fourth photoelectric conversion elements are arranged along a firstdirection, and wherein the second and the third photoelectric conversionelements are arranged along a second direction different from the firstdirection.
 10. The imaging device according to the claim 7, wherein thefirst, the second, the third, and the fourth photoelectric conversionelements are arranged along a first direction.
 11. The imaging deviceaccording to the claim 7, wherein the one of the pixel groups furtherincluding: a first reset transistor connected to the first floatingdiffusion; and a second reset transistor connected to the secondfloating diffusion.